Network Programming Initiative

Zerializer: Towards Zero-Copy Serialization

2021-07-29T00:00:00-04:00

Date: July 29, 2021
Time: 3:30-4:30pm ET

Abstract

Achieving zero-copy I/O has long been an important goal in the networking community. However, data serialization obviates the benefits of zero-copy I/O, because it requires the CPU to read, transform, and write message data, resulting in additional memory copies between the real object instances and the contiguous socket buffer. Therefore, we argue for off loading serialization logic to the DMA path via specialized hardware. We propose an initial hardware design for such an accelerator, and give preliminary evidence of its feasibility and expected benefits.

Bio

Adam Wolnikowski graduated from Yale in 2021 with a Bachelor’s in Electrical Engineering and Computer Science, and is now an embedded systems engineer at Humatics, a robotics startup in the Boston area. While at Yale, he researched both data center networking with Robert Soulé and attacks on machine learning accelerators with Jakub Szefer, and was awarded the Yale Computer Science Department prize for undergraduate research.

Petr4: Formal Foundations for P4 Data Planes

2021-02-23T00:00:00-05:00

Date: February 23, 2021
Time: 3:30-4:30pm ET

Video coming soon.

Abstract

Like many industrial languages, the P4 programming language has developed without a formal foundation. The P4 Language Specification is a 160-page document with a mixture of informal prose, graphical diagrams, and pseudocode; it leaves many aspects of program behavior up to individual compilation targets and compiler backends. The P4 reference implementation is a complex system, running to over 40KLoC of C++ code, with support for only a few targets. This talk presents a new framework, called Petr4, that puts the P4 programming language on a more solid semantic foundation. Petr4 consists of a clean-slate definitional interpreter and a core calculus that models a fragment of P4. Its semantics have been validated against existing test suites and the core calculus has been proved type-safe and terminating. While developing Petr4, we reported dozens of bugs in the language specification and the reference implementation, many of which have been fixed.

Bio

Ryan is a Ph.D. student at Cornell University where he is advised by Nate Foster. His research applies programming language techniques to computer networking problems.

NPI Retreat 2020

2020-12-11T00:00:00-05:00

OVERVIEW

The Network Programming Initiative (NPI) conducts annual Retreats to bring together faculty, students, postdocs, and industry partners for a one-day workshop with presentations, panels, and informal discussions related to network programming. Topics include practical use cases and solutions encompassing languages, algorithms and tools.

The Fall 2019 Retreat was held on Friday, October 11, 2019 in the Tata Innovation Center at the Cornell Tech campus on Roosevelt Island.

The Fall 2020 Retreat will be held on Friday, December 11, 2020 online via Zoom.

If you would like to attend, please remember RSVP’s are needed by Thursday, December 3rd at this link.

PROGRAM

1:00pm Welcome

1:15pm Reliability and Agility in Alibaba Global Network - Ennan Zhai (Alibaba)

Abstract: As one of the largest cloud service providers, Alibaba Cloud serves over one billion customers around the world. To ensure quality service at this scale, the underlying network infrastructure is of critical importance. This talk focuses on two of the essential aspects in our network management: reliability and agility. I will discuss recent examples of our efforts in these areas, including, first, our configuration verification system, Hoyan Jinjing, built to ensure the reliability of our global-scale network, and second, our new cutting-edge compiler, Lyra, designed to support flexible data plane programming on heterogeneous ASICs. In addition, I will also touch on our learned lessons and open questions in these areas.

1:30pm - 2:45pm Student Talks

1:30pm - Automatic optimization of endpoint packet-processing programs - Qiongwen Xu (Rutgers University)

Abstract: We are currently developing a program-synthesis-based compiler that performs automatic performance optimization of low-level packet-processing code. Given an instruction sequence, our compiler leverages the stochastic superoptimization framework [1] to search for a semantically equivalent instruction sequence which has higher performance than the input sequence. We have prototyped this compiler in the context of BPF [2], which is an in-kernel virtual machine instruction set that is deployed in several production systems, for example, to implement load balancing [3], DDoS protection [4], and container security policies [5].We have formalized the semantics of the BPF instruction set including domain-specific aspects such as memory access and key-value maps, and introduced several domain specific optimizations to reduce verification time by 4–5 orders of magnitude. Importantly, our optimization framework can incorporate safety conditions based on data flow, which is necessary for the programs to pass the in-kernel BPF static checker [2] and be executed in the kernel context. The development of this compiler is a work in progress. However, preliminary results are promising, with reliable performance improvements relative to clang -O3 for BPF programs from the kernel samples as well as programs currently run-on production systems.

1:40pm - Multitenancy for Fast and Programmable Networks in the Cloud - Tao Wang (NYU)

Abstract: Fast and programmable network devices are now readily available, both in the form of programmable switches and smart network-interface cards. Going forward, we envision that these devices will be widely deployed in the networks of cloud providers (e.g., AWS, Azure, and GCP) and exposed as a programmable surface for cloud customers similar to how cloud customers can today rent CPUs, GPUs, FPGAs, and ML accelerators. Making this vision a reality requires us to develop a mechanism to share the resources of a programmable network device across multiple cloud tenants. In other words, we need to provide multitenancy on these devices. To this end, we design compile and run-time approaches to multitenancy. We present preliminary results showing that our design provides both efficient resource utilization and isolation of tenant programs from each other.

1:50pm - Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on Heterogeneous ASICs - Jiaqi Gao (Harvard University)

Abstract: Programmable data plane has been moving towards deployments in data centers as mainstream vendors of switching ASICs enable programmability in their newly launched products, such as Broadcom’s Trident-4, Intel/Barefoot’s Tofino, and Cisco’s Silicon One. However, current data plane programs are written in low-level, chip-specific languages (e.g., P4 and NPL) and thus tightly coupled to the chip-specific architecture. As a result, it is arduous and error-prone to develop, maintain, and composite data plane programs in production networks. This paper presents Lyra, the first cross-platform, high-level language & compiler system that aids the programmers in programming data planes efficiently. Lyra offers a one-big-pipeline abstraction that allows programmers to use simple statements to express their intent, without laboriously taking care of the details in hardware; Lyra also proposes a set of synthesis and optimization techniques to automatically compile this “big-pipeline” program into multiple pieces of runnable chip-specific code that can be launched directly on the individual programmable switches of the target network. We built and evaluated Lyra. Lyra not only generates runnable real-world programs (in both P4 and NPL), but also uses up to 87.5% fewer hardware resources and up to 78% fewer lines of code than human-written programs.

2:00pm - RackSched: A Microsecond-Scale Scheduler for Rack-Scale Computers - Hang Zhu (JHU)

Abstract: Low-latency online services have strict Service Level Objectives (SLOs) that require datacenter systems to support high throughput at microsecond-scale tail latency. Dataplane operating systems have been designed to scale up multi-core servers with minimal overhead for such SLOs. However, as application demands continue to increase, scaling up is not enough, and serving larger demands requires these systems to scale out to multiple servers in a rack. We present RackSched, the first rack-level microsecond-scale scheduler that provides the abstraction of a rack-scale computer (i.e., a huge server with hundreds to thousands of cores) to an external service with network-system co-design. The core of RackSched is a two-layer scheduling framework that integrates inter-server scheduling in the top of-rack (ToR) switch with intra-server scheduling in each server. We use a combination of analytical results and simulations to show that it provides near-optimal performance as centralized scheduling policies and is robust for both low-dispersion and high-dispersion workloads. We design a custom switch data plane for the inter-server scheduler, which realizes power-of-k- choices, ensures request affinity, and tracks server loads accurately and efficiently. We implement a RackSched prototype on a cluster of commodity servers connected by a Barefoot Tofino switch. End-to-end experiments on a twelve-server testbed show that RackSched improves the throughput by up to 1.44x, and scales out the throughput near linearly, while maintaining the same tail latency as one server until the system is saturated.

2:10pm - Forwarding and Routing with Packet Subscriptions - Theo Jepsen (Stanford University)

Abstract: In this work, we explore how programmable data planes can naturally provide a higher-level of service to user applications via a new abstraction called packet subscriptions. Packet subscriptions generalize forwarding rules and can be used to express both traditional routing and more esoteric, content based approaches. We present strategies for routing with packet subscriptions in which a centralized controller has a global view of the network, and the network topology is organized as a hierarchical structure. We also describe a compiler for packet subscriptions that uses a novel BDD-based algorithm to efficiently translate predicates into P4 tables that can support O(100K) expressions. Using our system, we have built three diverse applications. We show that these applications can be deployed in brownfield networks while performing line-rate message processing, using the full switch bandwidth of 6.5Tbps.

2:20pm - Neptune: Balancing Flexibility, Performance, and Consistency on Heterogeneous Packet Processing Architectures - Praveen Kumar (Cornell University)

Abstract: Effectively using SmartNIC-based accelerators is challenging because of the fundamental trade-off between flexibility and performance. A promising approach is to use a heterogeneous architecture, but the difficulty of ensuring state consistency with distributed processing across the CPU and NIC adds another dimension to the trade-off. To harness the power of reconfigurable hardware, we present Neptune, a system that guarantees strong consistency while offering flexibility and hardware-level performance in the common case. Neptune features (i) a NIC architecture that flexibly accommodates a broad range of packet-processing tasks while providing state transactions and (ii) a CPU-based runtime system that maps packet processing onto this architecture and dynamically adapts to changing workloads. We present an FPGA-based implementation to show that Neptune flexibly accommodates a diverse set of applications with high 100 Gbps throughput and competitive 1 μs latency.

2:30pm - Elastic Switch Programming with P4All - Mary Hogan (Princeton University)

Abstract: The P4 language enables a range of new network applications. However, it is still far from easy to implement and optimize P4 programs for PISA hardware. Programmers must engage in a tedious “trial and error” process wherein they write their program (guessing it will fit within the hardware) and then check by compiling it. If it fails, they repeat the process. In this talk, we argue that programmers should define elastic data structures that stretch automatically to make use of available switch resources. We present P4All, an extension of P4 that supports elastic switch programming. Elastic data structures also make P4All modules reusable across different applications and hardware targets, where resource needs and constraints may vary. Our design is oriented around use of symbolic primitives (integers that may take on a range of possible values at compile time), arrays, and loops. We can use these primitive mechanisms to build a range of reusable libraries such as hash tables, Bloom filters, sketches, and key value stores. We will explain the important role that elasticity plays in modular programming, and we will show the P4All development process.

2:45pm - Technical Breakout Groups

Group 1 – Network Verification
Group 2 – In-Network Computing
Group 3 – Abstractions & Architectures
Group 4 – SmartNICs
Group 5 – Monitoring & Closed-Loop Control

3:15pm - Keynote + Q&A: The Accidental SmartNIC - Bruce Davie (VMWare)

Abstract: In 1989, a number of U.S. research institutions and universities started collaborating on a set of Gigabit testbeds - trying to build the first networks that could deliver data to and from applications at the seemingly crazy speed of 1Gbps. As part of the Aurora testbed, we built a number of flexible “host network interfaces” - flexible because we didn’t know what tasks would be done in the host and which should be offloaded. Our 1989 design - a couple of Intel CPUs, some big FPGAs, expensive optics - bore a striking similarity to the smartNICs of today. And in many ways, we still don’t know which tasks should be offloaded, which is why we continue to see CPUs and FPGAs on NICs - although some tasks like TCP header processing & tunneling for network virtualization are now well established as offloadable. This talk will examine the long-lived tradeoff between keeping network functions close to the application (in the host) and offloading them to the NIC in the hope of better performance and consider some of the implications of recent announcements of running a full hypervisor on the smartNIC.

Gauntlet: Finding Bugs in Compilers for Programmable Packet Processing

2020-09-29T00:00:00-04:00

Date: September 29, 2020
Time: 3:30-4:30pm ET

Abstract

Programmable packet-processing devices such as programmable switches and network interface cards are becoming mainstream. These devices are programmed in a domain-specific language such as P4, using a compiler to translate packet-processing programs into instructions for different targets. As networks with programmable devices become widespread, it is critical that these compilers are dependable.

This paper considers the problem of finding bugs in compilers for packet processing in the context of P4-16. We introduce domain-specific techniques to induce both abnormal termination of the compiler (crash bugs) and miscompilation (semantic bugs). We apply these techniques to (1) the open-source P4 compiler (P4C) infrastructure, which serves as a common base for different P4 back ends; (2) the P4 back end for the P4 reference software switch; and (3) the P4 back end for the Barefoot Tofino switch. Across the 3 platforms, over 4 months of bug finding, our tool Gauntlet detected 92 new and distinct bugs (58 crash and 34 semantic), which we confirmed with the respective compiler developers. 48 have been fixed (28 crash and 20 semantic); the remaining have been assigned to a developer. Our bug-finding efforts also led to 6 P4 specification changes. We have open sourced Gauntlet at https://github.com/p4gauntlet.

Bio

Fabian is a PhD student in the systems lab at New York University. He works with Anirudh Sivaraman on problems related to data center networking, more specifically programmable networks. Previously, he was a Master’s student in the Networks, Systems, and Security lab of the University of British Columbia, where he was advised by Ivan Beschastnikh.

SIGCOMM 2020: Preview 2

2020-07-30T00:00:00-04:00

Date: July 23, 2020
Time: 2:30-4:00pm ET

Agenda

2:30pm – 3:00pm

“Switch Code Generation using Program Synthesis”

Xiangyu Gao (NYU), Taegyun Kim (NYU), Michael Dean Wong (NYU), Divya Raghunathan (Princeton University), Aatish Kishan Varma (NYU), Pravein Govindan Kannan (National University of Singapore), Anirudh Sivaraman (NYU), Srinivas Narayana (Rutgers University).

3:00pm - 3:30pm

“BeauCoup: Answering Many Network Traffic Queries, One Memory Update at a Time”

Xiaoqi Chen (Princeton University), Shir Landau-Feibish (Princeton University), Mark Braverman (Princeton University), Jennifer Rexford (Princeton University).

3:30pm - 4:00pm

“NetLock: Fast, Centralized Lock Management Using Programmable Switches”

Zhuolong Yu (Johns Hopkins University), Yiwen Zhang (University of Michigan), Vladimir Braverman (Johns Hopkins University), Mosharaf Chowdhury (University of Michigan), Xin Jin (Johns Hopkins University).

SIGCOMM 2020: Preview 1

2020-07-23T00:00:00-04:00

Date: July 23, 2020
Time: 2:30-4:00pm ET

Agenda

2:30pm – 3:00pm

“Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on”Heterogeneous ASICs”

Jiaqi Gao (Alibaba Group and Harvard University), Ennan Zhai (Alibaba Group), Hongqiang Harry Liu (Alibaba Group), Rui Miao (Alibaba Group), Yu Zhou (Alibaba Group), Bingchuan Tian (Alibaba Group), Chen Sun (Alibaba Group), Dennis Cai (Alibaba Group), Ming Zhang (Alibaba Group), Minlan Yu (Harvard University).

3:00pm - 3:30pm

“PINT: Probabilistic In-band Network Telemetry”

Ran Ben Basat (Harvard University), Sivaramakrishnan Satyamangalam Ramanathan (University of Southern California), Yuliang Li (Harvard University), Gianni Antichi (Queen Mary University of London), Minlan Yu (Harvard University), Michael Mitzenmacher (Harvard University).

3:30pm - 4:00pm

“Composing Dataplane Programs with μP4”

Hardik Soni (Cornell University), Myriana Rifai (Nokia Bell Labs), Praveen Kumar (Cornell University), Ryan Doenges (Cornell University), Nate Foster (Cornell University).

Cheetah: Accelerating Database Queries with Switch Pruning

2020-06-25T00:00:00-04:00

Date: June 25, 2020
Time: 2:30-3:30pm ET

Abstract

Modern database systems are growing increasingly distributed and struggle to reduce query completion time with a large volume of data. In this paper, we leverage programmable switches in the network to partially offload query computation to the switch. While switches provide high performance, they have resource and programming constraints that make implementing diverse queries difficult. To fit in these constraints, we introduce the concept of data pruning – filtering out entries that are guaranteed not to affect output. The database system then runs the same query but on the pruned data, which significantly reduces processing time. We propose pruning algorithms for a variety of queries. We implement our system, Cheetah, on a Barefoot Tofino switch and Spark. Our evaluation on multiple workloads shows 40−200% improvement in the query completion time compared to Spark.

Bio

Syed is a second year PhD student at Harvard University advised by Dr. Minlan Yu. He has worked on problems involving programmable networks, cluster management, and the intersection of networking and database design.

Princeton P4 Campus: Building and Running Novel Campus Network Applications

2020-05-28T00:00:00-04:00

Date: May 28, 2020
Time: 2:30-3:30pm ET

Abstract

Doing impactful computer network research, which is applicable to real production networks, is hard. Lots of ideas remain unproven or are seen as unrealistic because they never get a chance to be validated on a production network. Meanwhile, network operators, who face and troubleshoot network issues every day, might be limited by using a familiar set of possibly outdated tools and practices for decades. P4 Campus is an initiative to help create, deploy, and run experimental but useful network applications on our production campus network. Through this talk we share our strategies, lessons learned, success stories, and our overall journey along the way. We hope other campuses can learn from our experience and join us on this journey. We believe that sharing our methods and practices for deploying programmable network applications can help other campus network operators and networking researchers identify shared goals and strengthen collaborations.

Bio

Joon Kim is an associate research scholar in the computer science department and a cyber infrastructure engineer at Princeton University. His current research focuses on building better network systems, applications, and tools with software-defined networking (SDN), programmable data planes, and P4. He is also enthusiastic about actually deploying such systems in a real network. His high-level goal is to make computer networks easier to monitor, secure, understand, and configure. He has received his Ph.D. and Masters degree in Computer Science from Georgia Tech under the supervision of Dr. Nick Feamster, and his Bachelor degree in Computer Science from the University of Wisconsin-Madison. He did several research internships at HP Labs in Palo Alto, USA. Prior to graduate school, he worked as a software engineer in South Korea for several years.

FlowDB: Towards a General, Scalable Framework for Fast Network Analytics

2020-04-23T00:00:00-04:00

Date: April 23, 2020
Time: 2:30-3:30pm ET

Abstract

Network analytics spans a wide range of important tasks and network researchers have developed a broad range of tools to conduct network analytics. To date, however, existing work has focused on point-solutions targeted at particular tasks (e.g. network configuration verification) or protocols (e.g., BGP). This lack of generality forces researchers to repeatedly reinvent the wheel as new use cases arise which existing tools do not quite cover. We address this problem by observing that fundamental network state data drawn from network devices can be naturally stored in database tables. These tables, however, do not map directly into traditional database data models since their entries can contain “wildcard expressions”; can contain actions (e.g., logic), and have a priority ordering. We therefore extend the traditional relational model to the network by introducing (i) the flow relation, a novel representation of a traditional relation which can efficiently capture network data, and (ii) the flow algebra, a systematic extension of the relational algebra over flow relations. In doing so, we bring both the generality of the relational model and its bevy of optimizations from the literature to network analytics. We realize this model by building the FlowDB. FlowDB can execute a wide variety of real network analytics tasks practiced by Facebook operators on two Facebook data centers with 10K+ switches and over 100 million rules in 50-70 seconds. FlowDB outperforms state-of-the-art analytics tools by more than 50x.

Bio

Christopher Leet graduated from Yale in 2018 with distinction in Computer Science and distinction in Astrophysics, winning Yale’s Beckwith prize for Astronomy. His research focuses on highly-scalable network analytics and large-scale multi-robot coordination.

Autogenerating Fast Packet-Processing Code Using Program Synthesis

2020-02-27T00:00:00-05:00

Date: February 27, 2020
Time: 2:30-3:30pm ET

Abstract

Packet-processing code should be fast. But, it is hard to write fast code for programmable substrates such as high-speed switches, multicore SoC SmartNICs, FPGAS, middleboxes, and the end-host stack. Today, expert developers with deep familiarity with the underlying hardware handcraft such code. Making things worse, building optimizing compilers for these substrates requires significant development effort, which may not be available for these new, niche, and evolving substrates. We propose an alternative: to automatically generate fast packet-processing code using program synthesis. For the domain of packet processing, leveraging program synthesis can generate faster code than optimizing compiler at the cost of increased compile time. As a case study, we apply program synthesis to build a code generator, Chipmunk, for a simulator of the protocol-independent switch architecture (PISA). Chipmunk generates code for many programs that a previous code generator based on classical compiler optimizations rejects, and code generated by Chipmunk uses much fewer hardware resources. We can also outline future directions in applying program synthesis to code generation for packet processing.

Bio

Xiangyu Gao is a PhD student at the Department of Computer Science, New York University, advised by Anirudh Sivaraman from New York University and Srinivas Narayana from Rutgers University. His research interest is in computer networks and programming language, with a focus on program synthesis and Domain specific algorithm design with application in programmable switches. Prior to NYU, he received his Bachelor’s degree from Shanghai University of Finance and Economics in 2013.

Network Programming Initiative

Zerializer: Towards Zero-Copy Serialization

Abstract

Bio

Petr4: Formal Foundations for P4 Data Planes

Abstract

Bio

NPI Retreat 2020

OVERVIEW

PROGRAM

1:00pm Welcome

1:15pm Reliability and Agility in Alibaba Global Network - Ennan Zhai (Alibaba)

1:30pm - 2:45pm Student Talks

1:30pm - Automatic optimization of endpoint packet-processing programs - Qiongwen Xu (Rutgers University)

1:40pm - Multitenancy for Fast and Programmable Networks in the Cloud - Tao Wang (NYU)

1:50pm - Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on Heterogeneous ASICs - Jiaqi Gao (Harvard University)

2:00pm - RackSched: A Microsecond-Scale Scheduler for Rack-Scale Computers - Hang Zhu (JHU)

2:10pm - Forwarding and Routing with Packet Subscriptions - Theo Jepsen (Stanford University)

2:20pm - Neptune: Balancing Flexibility, Performance, and Consistency on Heterogeneous Packet Processing Architectures - Praveen Kumar (Cornell University)

2:30pm - Elastic Switch Programming with P4All - Mary Hogan (Princeton University)

2:45pm - Technical Breakout Groups

3:15pm - Keynote + Q&A: The Accidental SmartNIC - Bruce Davie (VMWare)

4:00pm Social Activity

Gauntlet: Finding Bugs in Compilers for Programmable Packet Processing

Abstract

Bio

SIGCOMM 2020: Preview 2

Agenda

SIGCOMM 2020: Preview 1

Agenda

Cheetah: Accelerating Database Queries with Switch Pruning

Abstract

Bio

Princeton P4 Campus: Building and Running Novel Campus Network Applications

Abstract

Bio

FlowDB: Towards a General, Scalable Framework for Fast Network Analytics

Abstract

Bio

Autogenerating Fast Packet-Processing Code Using Program Synthesis

Abstract

Bio